1. Field
Exemplary embodiments of the present invention relate to an integrated circuit and a memory device, and more particularly, to an integrated circuit and a memory device to perform a boot-up operation for transmitting data from a nonvolatile memory to latch circuits.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a repair operation of a conventional memory device.
Referring to FIG. 1, the memory device includes a cell array 110 including a plurality of memory cells, a row circuit 120 for activating a word line selected by a row address R_ADD, and a column circuit 130 for accessing (reading or writing) data of a bit line selected by a column address C_ADD.
A row fuse circuit 140 stores a row address, which corresponds to a failed memory cell in the cell array 110, as a repair row address REPAIR_R_ADD. A row comparison unit 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 with a row address R_ADD inputted from an exterior of the memory device. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparison unit 150 controls the row circuit 120 to activate a redundancy word line instead of a word line designated by the row address R_ADD.
A column fuse circuit 160 stores a column address, which corresponds to a failed memory cell in the cell array 110, as a repair column address REPAIR_C_ADD. A column comparison unit 170 compares the repair column address REPAIR_C_ADD stored in the column fuse circuit 160 with a column address C_ADD inputted from the exterior of the memory device. When the repair column address REPAIR_C_ADD coincides with the column address C_ADD, the column comparison unit 170 controls the column circuit 130 to access a redundancy bit line instead of the bit line designated by the column address C_ADD.
The conventional fuse circuits 140 and 160 generally use a laser fuse. The laser fuse stores ‘high’ or ‘row’ data according to whether the fuse has been cut. The laser fuse is programmed at a wafer state of the memory device, but it is not possible to program the fuse after a wafer is mounted in a package. Also, it is not possible to design the laser fuse in a small area due because of pitch limitations.
In order to overcome such a problem, as disclosed in U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, one of nonvolatile memory circuits, such as an E-fuse array circuit, a NAND flash memory, a NOR flash memory, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), a FRAM (Ferroelectric RAM), or a MRAM (Magnetoresistive RAM), is included in the memory device, and repair information is stored in the nonvolatile memory circuit.
FIG. 2 is a block diagram illustrating a nonvolatile memory circuit storing repair information in a conventional memory device.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, latch circuits 210_0 to 210_3 provided in the memory banks BK0 to BK3 to store repair information, a latch circuit 210_4 for storing setting information a setting circuit 220, and a nonvolatile memory circuit 201.
The nonvolatile memory circuit 201 is a substitution of the fuse circuits 140 and 160. Repair information corresponding to all the banks BK0 to BK3, that is, a repair address is stored in the nonvolatile memory circuit 201. Setting information necessary for operation of the memory device is stored in the nonvolatile memory circuit 201. The nonvolatile memory circuit 201 may include either an E-fuse array circuit, a NAND flash memory, a NOR flash memory, an EPROM, an EEPROM, a FRAM, and/or a MRAM.
The latch circuits 210_0 to 210_3 store the repair information of the memory banks BK0 to BK3, respectively, and the latch circuit 210_4 stores setting information to be used in the setting circuit 220. The setting circuit 220 may perform an operation for setting various setting values necessary for an operation of the memory device, for example, internal voltage levels and various types of latency, by using the setting information stored in the latch circuit 210_4. The repair information is loaded from the nonvolatile memory circuit 201 to the latch circuits 210_0 to 210_3 after the memory device is powered on. The nonvolatile memory circuit 201 transmits stored repair information to the latch circuits 210_0 to 210_3 from the activation time point of a boot-up signal BOOTUP.
The nonvolatile memory circuit 201 is arranged as an array, and thus it takes a predetermined time to retrieve data stored in the nonvolatile memory circuit 201. Because of the predetermined time for data retrieval, it is not possible to promptly perform a repair operation by using the data stored in the nonvolatile memory circuit 201. For prompt operation, the repair information and the setting information stored in the nonvolatile memory circuit 201 is transmitted to the latch circuits 210_0 to 210_4 for storage, and data stored in the latch circuits 210_0 to 210_4 is used for repair operations of the memory banks BK0 to BK3 and setting operations of the setting circuit 220. A process in which the repair information and the setting information stored in the nonvolatile memory circuit 201 is transmitted to the latch circuits 210_0 to 210_4 is called a boot-up, and only when the boot-up operation is completed, the memory device can repair a failed cell, perform various setting operations, and then perform a normal operation (for example, a read/write operation).
As described above, in a memory device that stores the repair information and the setting information by using a nonvolatile memory circuit 201, the boot-up operation should be performed before a normal operation of the memory device. Therefore, data must be transmitted quickly and efficiently in a boot-up operation.